1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device that can operate in a normal operation mode, a read disturb test mode, and a burn-in test mode.
2. Description of the Background Art
FIG. 17 shows the entire structure of a semiconductor memory device including a dynamic random access memory (DRAM) with a read disturb test mode for detecting refresh error.
In read disturb testing, a read out operation is repeated for a constant time period with respect to one word line. A situation is created to facilitate data leakage from a memory cell connected to that word line. Data leakage is accelerated to detect refresh error. This read disturb testing is time consuming since it is generally carried out for all the word lines sequentially from word line WL1 to word line WLn (normal disturb testing).
A possible consideration for reducing the time required for testing is to select two or more row addresses at the same time such as word line WL1 and word line WL (n/2+1) and carry out a readout operation simultaneously (disturb accelerated test mode).
FIG. 18 shows a structure of a conventional semiconductor memory device that can operate in a normal operation mode and a burn-in test mode.
In general, a dynamic random access memory (DRAM) is subjected to an accelerated test mode (burn-in testing) wherein electrical stress is applied at a temperature higher than that of normal usage to eliminate any device that has the potential of initial defect prior to shipment of the product.
As shown in FIG. 18, a voltage that is down-converted with respect to an external power supply voltage is applied to internal circuitry such as memory cell array 3 in a normal operation mode in a DRAM including a voltage-down power supply unit 30. Since sufficient electrical stress cannot be applied to the internal circuitry such as memory cell array 3 in burn-in testing, the external power supply voltage is applied to the internal circuitry without reduction in burn-in testing.
However, power consumption due to the boosted potential consumed by the word line becomes greater than two times that of a conventional normal disturb test because a plurality of word lines are driven in response to two or more row addresses being selected simultaneously. There is a possibility that a word line is not boosted to a sufficient level in a read disturb test due to constrain in the power supply capability of a boosting power supply circuit 1 and another boosting power supply circuit 2 additionally provided for the test mode. In this case, the semiconductor memory device will operate erroneously, or will cause degradation in data retaining characteristics, if operated, to make it difficult to correlate with a normal disturb test.
In the conventional semiconductor memory device operating in a normal operation mode and a burn-in test mode shown in FIG. 18, a boosted voltage generated from a boosting power supply circuit 1 is applied to a word line driving circuit 7 and output circuit 6 as shown in FIG. 18. In a shared sense amplifier system in which a sense amplifier 4 disposed at the middle of a bit line is shared with two pairs of bit lines at either side thereof, a boosted voltage is applied from boosting power supply circuit 1 to select a bit line pair that is to be activated.
The level of the boosted voltage generated from boosting power supply circuit 1 varies according to difference in the process and temperature. It is difficult to control the boosted voltage during burn-in testing. There is a problem that sufficient stress cannot be applied to entire circuitry such as word line driving circuit 7 and output circuit 6 during a burn-in test mode to ensure acceleration.